An OFDM timing synchronization ASIC

Author

Johansson, Stefan ; Nilsson, Martin ; Nilsson, Peter

Author_Institution

Dept. of Appl. Electron., Lund Univ., Sweden

Volume

1

fYear

2000

fDate

2000

Firstpage

324

Abstract

In this paper an OFDM timing synchronization ASIC is presented. The proposed synchronization unit can be used in any OFDM system. The algorithm is based on the correlation introduced by the cyclic prefix, which is exploited in the time domain where the time offset is estimated. Although the algorithm is too complex to be implemented on today´s most powerful standard DSP, a hardware architecture that is optimized for the algorithm is implemented with moderate complexity. The unit contains 32 kbit RAM and 3000 gates. At the sample rate of 25 Msamples/s the power consumption is 16 mW, which is small for such a complex algorithm

Keywords

CMOS digital integrated circuits; OFDM modulation; application specific integrated circuits; digital signal processing chips; synchronisation; telecommunication computing; telecommunication equipment; timing; 0.35 micron; 16 mW; 32 kbit; DSP; OFDM timing synchronization ASIC; correlation; cyclic prefix; hardware architecture; synchronization unit; time offset estimation; Application specific integrated circuits; Digital signal processing; Energy consumption; Frequency estimation; Frequency synchronization; Land mobile radio; Maximum likelihood estimation; OFDM modulation; Phase modulation; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on

Conference_Location

Jounieh

Print_ISBN

0-7803-6542-9

Type

conf

DOI

10.1109/ICECS.2000.911547

Filename

911547