DocumentCode
1743369
Title
Frame detection in high bit-rate CMOS systems
Author
de Vasconcelos, Eduardo ; Aguiar, Rui L.
Author_Institution
Dept. de Electron. e Telecoms, Aveiro Univ., Portugal
Volume
1
fYear
2000
fDate
2000
Firstpage
328
Abstract
This paper presents a technique for frame synchronization in high-speed telecommunications systems. The described structure allows frame synchronization to be performed independently from the technology inherent delays, resorting to a parallel data pattern detector and a bit alignment shifter. The principle has been implemented in a 0.8 μm CMOS SDH/STM-4 (622 Mb/s) system
Keywords
CMOS digital integrated circuits; digital communication; high-speed integrated circuits; synchronisation; synchronous digital hierarchy; timing; 622 Mbit/s; SDH/STM-4 system; bit alignment shifter; frame detection; frame synchronization; high bit-rate CMOS systems; high-speed telecommunications systems; parallel data pattern detector; CMOS technology; Circuits; Clocks; Control systems; Delay; Detectors; Frequency synchronization; Production systems; Synchronous digital hierarchy; Telecommunications;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on
Conference_Location
Jounieh
Print_ISBN
0-7803-6542-9
Type
conf
DOI
10.1109/ICECS.2000.911548
Filename
911548
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