A VLSI architecture of 2D wavelet transforms

Author

Achour, C. ; Houle, J.-L. ; Davidson, J.

Author_Institution

Ecole Polytech. de Montreal, Que., Canada

Volume

1

fYear

2000

fDate

2000

Firstpage

370

Abstract

This paper presents a new implementation of a 2D wavelet transform in a VLSI circuit, for real-time digital signal processing. The parallel algorithm of the 2D wavelet transform (2D-WT) used for designing and implementing this new architecture enhances the performance of computations. The proposed multi-elementary processor architecture of 2D-WT yields a very flexible hardware configuration. This approach offers a high processing speed, relative to other methods, for providing the wavelet coefficients. The 2D-WT is a powerful tool for several applications, the most important one being image processing

Keywords

CMOS digital integrated circuits; VLSI; digital signal processing chips; image processing equipment; parallel algorithms; parallel architectures; real-time systems; wavelet transforms; 0.35 micron; 2D wavelet transforms; DSP; VLSI architecture; flexible hardware configuration; high processing speed; image processing; multi-elementary processor architecture; parallel algorithm; real-time digital signal processing; wavelet coefficient; Algorithm design and analysis; Circuits; Computer architecture; Concurrent computing; Digital signal processing; Hardware; Parallel algorithms; Very large scale integration; Wavelet coefficients; Wavelet transforms;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on

Conference_Location

Jounieh

Print_ISBN

0-7803-6542-9

Type

conf

DOI

10.1109/ICECS.2000.911558

Filename

911558