Title :
On efficient CPU-usage in a VLSI CAD-environment with application to circuit partitioning
Author :
Wichlund, Sverre ; Aas, Einar J.
Author_Institution :
Nordic VLSI ASA, Tiller, Norway
Abstract :
We show experimentally that the number of clustering levels in a multilevel circuit partitioning algorithm may be reduced if guided by a measure of regularity applied to the input circuit netlist. Furthermore, we devise a simple tactic to reduce the number of runs in a multistart circuit partitioning algorithm. As a consequence CPU-time is saved. This comes at only a minor degradation in solution cost. Experiments were performed by applying our algorithm MLAF to the ISPD-98 benchmarks
Keywords :
VLSI; circuit CAD; circuit layout CAD; integrated circuit design; MLAF algorithm; VLSI CAD environment; circuit partitioning; clustering levels reduction; efficient CPU-usage; input circuit netlist; multilevel circuit partitioning algorithm; multistart circuit partitioning algorithm; Benchmark testing; Circuit testing; Clustering algorithms; Computer science; Cost function; Degradation; Packaging; Partitioning algorithms; Predictive models; Very large scale integration;
Conference_Titel :
Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on
Conference_Location :
Jounieh
Print_ISBN :
0-7803-6542-9
DOI :
10.1109/ICECS.2000.911569
