Energy consumption minimisation with new synthesis method

Author

Brzozowski, Ireneusz ; Kos, Andrzej

Author_Institution

Inst. of Electron. AGH, Krakow, Poland

Volume

1

fYear

2000

fDate

2000

Firstpage

605

Abstract

The paper deals with a logic synthesis method, which leads to minimisation of energy consumed by integrated digital circuits thanks to the decrease of switching activity. As a consequence, less complicated, smaller, more reliable and faster digital circuits can be obtained. The hypothetical circuits were proposed, simulated, fabricated in CMOS technology and tested. The examples show that we are able to save significant amounts of energy

Keywords

CMOS digital integrated circuits; application specific integrated circuits; circuit optimisation; integrated circuit design; integrated circuit testing; logic design; logic simulation; low-power electronics; CMOS technology; circuit simulation; energy consumption minimisation; integrated digital circuits; logic synthesis; reliable fast digital circuits; switching activity decrease; test ASIC; CMOS logic circuits; CMOS technology; Circuit testing; Digital circuits; Energy consumption; Integrated circuit reliability; Integrated circuit synthesis; Logic circuits; Minimization methods; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on

Conference_Location

Jounieh

Print_ISBN

0-7803-6542-9

Type

conf

DOI

10.1109/ICECS.2000.911612

Filename

911612