High performance level restoration circuits for low-power reduced-swing interconnect schemes

Two high performance level restoration circuits are proposed, which outperform the existing level restoration circuits with cross-coupled PMOS, in terms of power dissipation and delay. The first configuration employs a back-bias scheme in order to eliminate the stand-by leakage caused by the low-swing input. The second one adopts a bootstrapping technique, in order to restore the low swing signal, without dc power consumption. By applying one of the proposed level restoration circuits as a receiver in a low-swing interconnect scheme, a 60% power reduction and 50% power delay product improvement can be achieved, when compared to the conventional full-swing design