Title :
Delay analysis of neuron-MOS and capacitive threshold-logic
Author :
Celinski, Peter ; Al-Sarawi, Said ; Abbott, Derek
Author_Institution :
Dept. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia
Abstract :
A model for the delay of neuron-PMOS (neu-MOS) and Capacitive Threshold-Logic (CTL) based logic circuits is presented for the first time. It is based on the analysis of the basic neuron-MOS and CTL gate structures. A closed form analytic expression for the delay of the threshold gate is derived. A relation for the delay in terms of an ordinary CMOS inverter delay expressed as a function of the number of inputs to the threshold gate is presented. This relation is shown to be useful in comparing the delay of logic circuit designs based on neu-MOS or CTL and ordinary CMOS
Keywords :
MOS logic circuits; delays; logic gates; neural chips; threshold elements; CTL gate structures; capacitive threshold-logic; closed form analytic expression; inverter delay; logic circuit designs; neuron-PMOS logic circuits; Boolean functions; CMOS logic circuits; Circuit testing; Delay effects; Input variables; Inverters; Logic circuits; Logic gates; Neurons; Silicon;
Conference_Titel :
Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on
Conference_Location :
Jounieh
Print_ISBN :
0-7803-6542-9
DOI :
10.1109/ICECS.2000.913029
