Test insertion at the RT level using functional test metrics

Author

Harmanani, Haidar ; Harfoush, Salam

Author_Institution

Dept. of Comput. Eng. & Sci., Lebanese American Univ., Byblos, Lebanon

Volume

2

fYear

2000

fDate

2000

Firstpage

1016

Abstract

A new method of redesign for testability at the Register-Transfer Level (RTL) is proposed. The method identifies hard to test parts of a an RTL design synthesized either manually or automatically using high-level synthesis tools. The design is modified by inserting additional test registers followed by a test selection process. During the selection process, two test metrics are used in order to minimize test overhead. Finally, test scheduling is performed so that to minimize the overall test time and the number of test sessions. The system outputs a VHDL description of a testable data path along with a test plan

Keywords

VLSI; built-in self test; design for testability; digital integrated circuits; high level synthesis; integrated circuit testing; logic testing; scheduling; BIST; RT level test insertion; RTL design; VHDL description; additional test registers; functional test metrics; high-level synthesis tools; redesign for testability; register-transfer level; test metrics; test overhead minimisation; test plan; test scheduling; test selection process; testable data path; Automatic testing; Built-in self-test; Circuit testing; Costs; Design for testability; Logic testing; Pattern analysis; Registers; Scheduling; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on

Conference_Location

Jounieh

Print_ISBN

0-7803-6542-9

Type

conf

DOI

10.1109/ICECS.2000.913048

Filename

913048