DocumentCode :
1744280
Title :
Modeling crosstalk noise for deep submicron verification tools
Author :
Sabet, Pirouz Bazargan ; Ilponse, Fabrice
Author_Institution :
Paris VI Univ., France
fYear :
2001
fDate :
2001
Firstpage :
530
Lastpage :
534
Abstract :
In deep submicron technologies, the verification task has to cover some new issues to certify the correctness of a design. The noise produced by crosstalk couplings is one of these emerging problems. In this paper, we propose a model to evaluate the peak value of the noise injected on a signal when its neighboring signals make their transitions. This model has been used in a prototype verification tool and has shown a satisfying performance-accuracy ratio
Keywords :
VLSI; capacitance; circuit layout CAD; crosstalk; integrated circuit layout; integrated circuit modelling; integrated circuit noise; crosstalk noise modeling; deep submicron verification tools; design correctness verification; prototype verification tool; Capacitance; Circuit noise; Circuit simulation; Coupling circuits; Crosstalk; Delay estimation; Process design; Prototypes; Steady-state; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings
Conference_Location :
Munich
ISSN :
1530-1591
Print_ISBN :
0-7695-0993-2
Type :
conf
DOI :
10.1109/DATE.2001.915074
Filename :
915074
Link To Document :
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