Low power order based DCT processing algorithm

This paper presents an algorithm and an associated architecture for the low power implementation of the Discrete Cosine Transform. The algorithm reduces power by manipulating bit-correlation between successive cosine coefficients applied to the input of the Multiply-Accumulate section such that the effective switched capacitance is reduced. This reduces the switching activity in the Discrete Cosine Transform processor. The paper describes the algorithm and the proposed architecture. The evaluation procedure is also presented including the results from a number of example images illustrating up-to 29%, power savings