DocumentCode
1744793
Title
Scalable module-based architecture for MPEG-4 BMA motion estimation
Author
Hsu, Mei-Yuiz ; Hao-Chieh Chang ; Wang, Yi-Chu ; Chen, Liang-Gee
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume
2
fYear
2001
fDate
6-9 May 2001
Firstpage
245
Abstract
In this paper, we present a scalable module-based architecture for block matching motion estimation algorithm of MPEG-4. The basic module comprises one set of processing elements based on one-dimensional systolic array architecture. To support various applications, modules of processing elements can be configured to form the processing element array to meet the requirements, such as variable block size, search range and computation power. And this proposed architecture has the advantage of few I/O port counts. Based on eliminating unnecessary signal transitions in the processing element, power dissipation of datapath can be reduced to about half without decreasing the picture quality
Keywords
image matching; motion estimation; systolic arrays; MPEG-4; block matching algorithm; datapath; motion estimation; one-dimensional systolic array; picture quality; power dissipation; processing element module; scalable architecture; signal transition; Algorithm design and analysis; Computer architecture; Digital signal processing; Hardware; MPEG 4 Standard; Motion estimation; Power dissipation; Registers; Signal processing; Systolic arrays;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location
Sydney, NSW
Print_ISBN
0-7803-6685-9
Type
conf
DOI
10.1109/ISCAS.2001.921053
Filename
921053
Link To Document