DocumentCode
1744857
Title
Sampling-rate optimization of an interleaved-sampling front-end
Author
Johansson, Henrik O. ; Horowitz, Mark
Author_Institution
Comput. Syst. Lab., Stanford Univ., CA, USA
Volume
2
fYear
2001
fDate
6-9 May 2001
Firstpage
573
Abstract
Interleaved sampling is an often used way to attain high aggregate sampling-rates. There are several physical effects that may limit the useful aggregate sampling rate. In this paper some of these effects are addressed and their trade-offs are investigated with mathematical models and optimization algorithms to maximize this sampling rate
Keywords
CMOS integrated circuits; analogue-digital conversion; optimisation; sample and hold circuits; signal sampling; aggregate sampling rate; interleaved-sampling front-end; mathematical models; optimization algorithms; sampling-rate optimization; Aggregates; Attenuation; Capacitance; Circuits; Clocks; Filtering; Low pass filters; Mathematical model; Sampling methods; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location
Sydney, NSW
Print_ISBN
0-7803-6685-9
Type
conf
DOI
10.1109/ISCAS.2001.921135
Filename
921135
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