An efficient 0-1 linear programming for optimal PLA folding

Author

Raahemifa, Kaamran ; Ahmadi, Majid

Author_Institution

Dept. of Electr. & Comput. Eng., Ryerson Polytech. Univ., Toronto, Ont., Canada

Volume

2

fYear

2001

fDate

6-9 May 2001

Firstpage

581

Abstract

In this paper we propose a new 0-1 integer linear formulation for optimal PLA folding. An efficient heuristic algorithm is presented which finds optimal PLA folding in polynomial time. The algorithm finds the maximum matching of a given green-edge graph. Then, directions are assigned to each selected edge to minimize a certain objective function on a red-edge graph. The existing alternating cycles are verified and eliminated. Finally, the coordinates of each interconnection of PLA are computed. Test results show that the algorithm is efficient and gives the optimal solutions for most cases

Keywords

VLSI; circuit layout CAD; graph theory; high level synthesis; integrated circuit layout; linear programming; network topology; programmable logic arrays; 0-1 linear programming; efficient heuristic algorithm; green-edge graph; integer linear formulation; interconnection coordinates; maximum matching; objective function; optimal PLA folding; polynomial time; red-edge graph; Equations; Heuristic algorithms; Linear programming; Logic arrays; Logic design; Logic functions; Polynomials; Programmable logic arrays; Testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.921137

Filename

921137