New architectures for serial-serial multiplication

Traditional serial-serial multiplier structures suffer from an inefficient generation of partial products, which leads to hardware overuse and slow speed systems. In this paper, two new architectures for fully serial multiplication are presented. To the best of our knowledge, the first structure is the first fully serial multiplier reported in the literature with comparable performance-in terms of speed-to existing serial-parallel multipliers. The second structure requires an extra multiplexer in the clock path thus making it slower, but has the merit of reducing the latency of the multiplier. Both structures are systolic and need near communication links only. Compared with available architectures, an FPGA based implementation has shown an increase in the speed of the multipliers by about 200% for the first structure and 150% for the second structure