Title :
MOS fully analog reinforcement neural network chip
Author :
Al-Nsour, Mahmoud ; Abdel-Aty-Zohdy, Hoda S.
Author_Institution :
Microelectron. Syst. Design Lab., Oakland Univ., Rochester, MI, USA
Abstract :
This paper addresses the design and implementation of an analog MOS reinforcement neural network by compact and novel subcircuits. System implementation was optimized for minimum silicon area and maximum input signal swing. The chip, consisting of two three-input neurons, is designed and implemented using 1.5 μm CMOS n-well technology and occupied 0.114 mm2. Due to the limited number of pads on a TinyChip, only two neurons were implemented. The ANN system is to be used for gas recognition applications, with present off-chip learning. Learning through digital genetic algorithms implementation is successfully achieved, and will be further implemented in silicon for integrated system-on-a-chip
Keywords :
CMOS analogue integrated circuits; VLSI; analogue multipliers; genetic algorithms; integrated circuit design; learning (artificial intelligence); neural chips; 0.114 mm; CMOS n-well technology; MAGIC layout; TinyChip; VLSI; analog MOS adder; analog MOS reinforcement neural network; complex subcircuits; digital genetic algorithms; four quadrant analog multiplier; fully analog reinforcement neural network chip; gas recognition applications; integrated system-on-a-chip; maximum input signal swing; minimum silicon area; neural chip design; off-chip learning; optimized system implementation; sigmoid function circuit; standard cell components; three-input neurons; voltage mode design; Adders; Artificial neural networks; Biological neural networks; Circuits; Laboratories; MOSFETs; Neural networks; Neurons; Silicon; Voltage;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.921291
