Title :
Hardware combinatorial optimization problems solver by hysteresis neural networks
Author :
Nakaguchi, Toshiya ; Jin´no, Kenya ; Tanaka, Mamoru
Author_Institution :
Sophia Univ., Tokyo, Japan
Abstract :
Hysteresis neural network is applied to combinatorial optimization problems and efficiency of its parallel computing is obtained by numerical calculations. In this research, we implement hardware optimization problems solver by hysteresis neural networks. To produce hysteresis neural module, we propose a novel synapse architecture. From experimental results, we confirm the efficiency of implementation
Keywords :
neural nets; optimisation; parallel architectures; problem solving; hardware combinatorial optimization problems solver; hysteresis neural networks; implementation efficiency; numerical calculations; parallel computing; synapse architecture; Computer architecture; Convergence of numerical methods; Differential equations; Hysteresis; Neural network hardware; Neural networks; Parallel processing; Piecewise linear techniques; Stability; Vectors;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.921373
