A 2.5 Gbit/s CMOS PLL for data/clock recovery without frequency divider

Author

Tang, Yonghui ; Geiger, Randall L.

Author_Institution

Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA

Volume

1

fYear

2001

fDate

6-9 May 2001

Firstpage

256

Abstract

A phase locked loop (PLL) design based on a new phase detector (PD) is presented. It can be used as a part of data/clock recovery (DCR) systems targeting the applications of 2 Gbit/s-3 Gbit/s range Ethernet and optic fiber transceivers in current semiconductor processes. A key component in the circuit is a new non-sequential PD that provides for very high speed operation. Using TSMC 0.25 u CMOS process device models and the HSPICE simulator, results show that the PLL can operate at 2.5 GHz over process corners and a 0°C to 100°C temperature range. Total power dissipation is 40 mW with a single 2.5 V power supply

Keywords

CMOS integrated circuits; SPICE; circuit simulation; local area networks; optical communication equipment; phase detectors; phase locked loops; synchronisation; transceivers; 0 to 100 degC; 0.25 micron; 2.5 Gbit/s; 2.5 V; 40 mW; CMOS PLL; Ethernet; HSPICE simulator; data/clock recovery; nonsequential PD; optic fiber transceivers; phase detector; power dissipation; Circuits; Clocks; Detectors; Ethernet networks; Frequency; High speed optical techniques; Optical fiber devices; Phase detection; Phase locked loops; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.921839

Filename

921839