Fast-locking low-jitter integrated CMOS phase-locked loop

In this paper we present a new topology of fast-locking low-jitter phase-locked loop (PLL). The proposed PLL is based on frequency-to-voltage converters (FVCs) to convert the PLL reference and oscillating frequencies (Fref and Fosc) to respective voltages. These voltages are then compared by two transconductance operational amplifiers (OTAs) and their output currents are used to adjust the PLL charge-pump currents. As a consequence, the PLL speed will be automatically tuned when the difference between Fref and Fosc is large. To reduce the PLL phase noise or jitter, an improved phase/frequency detector (PFD), a charge pump (CHP) as well as a differential voltage-controlled oscillator (VCO) are used in this application. Simulation results are very attractive and improve significantly the theoretical approach