Title :
A high-speed frequency up-translated SC bandpass filter with auto-zeroing for DDFS systems
Author :
U, Seng-Pan ; Martins, R.P. ; Franca, J.E.
Author_Institution :
Fac. of Sci. & Technol., Macau Univ., China
Abstract :
This paper presents the design and implementation of a 160 Msample/s output, offset-compensated, linear-phase, frequency uptranslated Switched-Capacitor bandpass filter with 28.5 MHz midband frequency for a DDFS system. This bandpass system translates the 40 Msample/s, 11-12 MHz bandwidth signals from DDFS output to a higher 160 Msample/s, 28-29 MHz outputs with a 40 dB rejection of the unwanted frequency-translated signal bands. Special considerations and design in both circuit architectures and layout arrangements for dealing with non-ideal properties in realization of the high-speed analog and digital clock circuits will be discussed in terms of the speed relaxation, noise and mismatching reduction. The system is designed with 0.35 μm CMOS technology and verified by behavioral, transistor-level and layout-extracted simulations. The active layout area occupies about 1.3 mm ×2.7 mm and the circuit consumes about 138 mW for analog and 32 mW for digital at 3.0 V supply
Keywords :
CMOS integrated circuits; band-pass filters; direct digital synthesis; frequency convertors; high-speed integrated circuits; linear phase filters; switched capacitor filters; 0.35 micron; 11 to 12 MHz; 138 mW; 28.5 MHz; 3.0 V; 32 mW; CMOS technology; DDFS system; auto-zeroing; high-speed frequency up-translation; linear phase filter; offset compensation; switched capacitor bandpass filter; Band pass filters; Bandwidth; CMOS technology; Circuits; Clocks; Electronic mail; Filtering; Frequency synthesizers; Interpolation; Sampling methods;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.921857
