Title :
Multirate-cascade sigma-delta (MC-SD) modulators
Author :
Torralba, A. ; Colodro, F.
Author_Institution :
Seville Univ., Spain
Abstract :
New high-speed sigma-delta (SD) analog to digital converters (ADC´s) are required for xDSL and RF receivers. As sampling frequency is upper limited by the amplifier bandwidth and power consumption, these high-speed, low-power converters operate with a small oversampling ratio. Usually, they are high-order cascade structures with a multibit quantizer in the last stage. All previously reported approaches use a unique sampling frequency. This paper shows that multirating is a useful technique to reduce power consumption in high speed SD converters. To this end, a multirate-cascade SD modulator is proposed where a low oversampling frequency is used in the first stage(s) of a cascade converter
Keywords :
CMOS integrated circuits; cascade networks; circuit stability; high-speed integrated circuits; low-power electronics; modulators; sigma-delta modulation; RF receivers; analog to digital converters; high-speed sigma-delta ADC; low oversampling frequency; low-power converters; multirate-cascade sigma-delta modulators; oversampling ratio; power consumption reduction; sampling frequency; xDSL; Analog-digital conversion; Bandwidth; Baseband; Clocks; Delta-sigma modulation; Energy consumption; Frequency conversion; Parasitic capacitance; Sampling methods; Topology;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.921873
