Title :
A high-speed subranging system with background equalization of the sampling instants
Author :
Quilligan, G. ; Burton, D.P.
Author_Institution :
Limerick Univ., Ireland
Abstract :
The front-end sample-hold amplifier of a CMOS analog-digital converter can be made subranging, resulting in decreased output swing, by combining it with a residue amplifier function and directly quantizing the input. A control-loop minimizes the sampling instant mismatch by adjusting the timing to the coarse quantizer´s clock input using the sign of the input signal´s first order derivative. The process operates completely in the background with no specialized input signal for calibration
Keywords :
CMOS integrated circuits; analogue-digital conversion; equalisers; sample and hold circuits; timing; CMOS ADC; analog-digital converter; background equalization; coarse quantizer clock input; control-loop; front-end sample-hold amplifier; high-speed subranging system; residue amplifier function; sampling instants; timing; Analog-digital conversion; CMOS process; Calibration; Capacitors; Clocks; Delay; Sampling methods; Signal processing; Timing; Voltage;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.921881
