DocumentCode :
1745136
Title :
A compensation technique for integrator´s pole error in cascaded sigma-delta modulators
Author :
Yedevelly, Yeshoda ; Chao, Kwong-Shu ; Fang, Lieyi
Author_Institution :
Lucent Technol. Bell Labs., Holmdel, NJ, USA
Volume :
1
fYear :
2001
fDate :
6-9 May 2001
Firstpage :
444
Abstract :
The integrator leakage (pole) error affects the performance of sigma-delta modulators. A solution for reducing the integrator pole error based on the concept of positive feedback is proposed. A MASH structure employing such a compensated integrator is analyzed and results are verified by both system and circuit level simulations
Keywords :
SPICE; cascade networks; error compensation; feedback amplifiers; integrating circuits; operational amplifiers; quantisation (signal); sigma-delta modulation; switched capacitor networks; CMOS process; MASH structure; SPICE; cascaded sigma-delta modulators; circuit level simulation; compensated integrator; compensation technique; finite op amp gain; higher-order noise shaping; integrator leakage error; integrator pole error; positive feedback; quantization noise; system level simulation; transfer functions; Capacitors; Computer errors; Delta-sigma modulation; Feedback; Instruments; Multi-stage noise shaping; Noise shaping; Operational amplifiers; Quantization; Transfer functions;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
Type :
conf
DOI :
10.1109/ISCAS.2001.921888
Filename :
921888
Link To Document :
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