Built-In self-repair for divided word line memory

Author

Lu, Shyue-Kung ; Hsu, Chih-Hsien

Author_Institution

Dept. of Electron. Eng., Fe-Jen Catholic Univ., Taipei, Taiwan

Volume

4

fYear

2001

fDate

6-9 May 2001

Firstpage

13

Abstract

In this paper, a novel block-repair fault-tolerant architecture based on the characteristics of divided word line (DWL) is proposed for high-capacity memories. We divide the memory cell array into blocks and redundancies are added at the block level. Our fault-tolerant architecture can improve the yield for memory fabrication significantly. According to experimental results, the hardware overheads are less than 0.732% and 0.48% for SRAMs and DRAMs, respectively, It also concludes that the block repair approach improves repair rate significantly

Keywords

DRAM chips; SRAM chips; cellular arrays; fault tolerance; integrated circuit yield; memory architecture; redundancy; DRAMs; SRAMs; block-repair fault-tolerant architecture; built-in self-repair; divided word line memory; hardware overheads; high-capacity memories; memory cell array; redundancies; repair rate; yield; Circuit faults; Fabrication; Fault tolerance; Hardware; Memory architecture; Power dissipation; Power generation; Random access memory; Redundancy; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922156

Filename

922156