DocumentCode
1745203
Title
Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design
Author
Chien-Hsing Wu ; Chien-Ming Wu ; Shieh, Ming-Der ; Hwang, Yin-Tsung
Author_Institution
Dept. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol, Taiwan
Volume
4
fYear
2001
fDate
6-9 May 2001
Firstpage
33
Abstract
We present a parallel-in parallel-out systolic division circuit over GF(2m) based on the novel extended Stein´s algorithm that provides guaranteed convergence in 2m-1 iterations. The area-time (AT) complexity of our design is O(m2) and the achievable maximum clock rate is 1 GHz based on the 0.6 μm technology. Compared to the best systolic design known to date based on the extended Euclid´s algorithm the proposed circuit exhibits significant area and speed advantages
Keywords
Galois fields; VLSI; circuit complexity; digital arithmetic; dividing circuits; high-speed integrated circuits; iterative methods; systolic arrays; 0.6 micron; 1 GHz; GF(2m); area-time complexity; clock rate; convergence; extended Euclid algorithm; extended Stein algorithm; high-speed low-complexity design; iterative division algorithm; modular arithmetic; parallel-in parallel-out systolic VLSI circuit; Algorithm design and analysis; Circuits; Clocks; Design engineering; Error correction; Galois fields; Iterative algorithms; Polynomials; Public key cryptography; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location
Sydney, NSW
Print_ISBN
0-7803-6685-9
Type
conf
DOI
10.1109/ISCAS.2001.922162
Filename
922162
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