PN-generators embedded in high performance signal processors

Wireless systems based on CDMA such as proposed in the 3GPP standard utilize pseudo random number sequences for generation of the spreading codes. These sequences are usually created by the use of finite field arithmetic. A pure software implementation onto a digital signal processor (DSP) is very inefficient and would result in unreasonable high computational load. In this paper a hardware-based scheme is proposed which allows for an efficient implementation on a high performance DSP as well as into an ASIC. With the configurable approach a binary PN-sequence with an arbitrary primitive polynomial can be generated. The unit was specially designed for and embedded into a domain specific processor, which supports W-CDMA and alike baseband processing