VLSI architecture design and implementation for BLOWFISH block cipher with secure modes of operation

Author

Lai, Yeong-Kang ; Shu, Yu-Chuan

Author_Institution

Dept. of Corp. Sci. & Inf. Eng., Nat. Dong-Hua Univ., Taiwan

Volume

4

fYear

2001

fDate

6-9 May 2001

Firstpage

57

Abstract

In this paper, a novel VLSI architecture of the BLOWFISH block cipher is presented. Based on the loop-folding technique combined with secure modes (ECB, CBC2, CFB2 and OFB2) of operation, the architecture can make data encryption/decryption more efficient and secure. To demonstrate the correctness of our design, a prototype chip for the architecture has been implemented by using 0.35 μ CMOS technology. The chip can achieve an encryption rate of 288 Mb/a and consume 32.7 mW while operating at a 72 MHz clock rate. Therefore, the chip can be applied to on-line encryption in high-speed networking protocols like ATM networks

Keywords

CMOS digital integrated circuits; VLSI; asynchronous transfer mode; block codes; cryptography; protocols; 0.35 micron; 288 Mbit/s; 37.2 mW; 72 MHz; ATM networks; BLOWFISH block cipher; CMOS technology; VLSI architecture design; data encryption; decryption; high-speed networking protocols; loop-folding technique; secure modes of operation; CMOS technology; Computer architecture; Cryptography; Data security; Databases; Mobile communication; Output feedback; Protection; Telecommunication computing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922168

Filename

922168