A 2.5 Mb/s, 23 mW SOVA traceback chip for turbo decoding applications

Author

Garrett, David ; Stan, Mircea

Author_Institution

Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA

Volume

4

fYear

2001

fDate

6-9 May 2001

Firstpage

61

Abstract

This paper presents a novel implementation of a low power architecture for the soft-output Viterbi algorithm (SOVA), a building block for turbo codes. The architecture builds on previous work on the Viterbi algorithm (VA) and SOVA, and incorporates a novel orthogonal access memory structure which allows received information to remain static while it feeds the underlying traceback pipeline. Ultimately, the work shows a feasible implementation of a 42-stage traceback pipeline for SOVA running with a traceback throughput of 7.5 Mb/s at 54 mW

Keywords

CMOS digital integrated circuits; Viterbi decoding; low-power electronics; pipeline processing; systolic arrays; turbo codes; 2.5 Mbit/s; 23 mW; 54 mW; 7.5 Mbit/s; SOVA traceback chip; low power architecture; orthogonal access memory structure; soft-output Viterbi algorithm; traceback pipeline; traceback throughput; turbo codes; turbo decoding applications; Channel capacity; Error correction codes; Feeds; Iterative decoding; Maximum likelihood decoding; Memory management; Pipelines; Throughput; Turbo codes; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922169

Filename

922169