Title :
A 1.25 GHz 32-bit tree-structured carry lookahead adder
Author :
Wang, Chua-Chin ; Lee, Po-Ming ; Lee, Roizg-Chin ; Huang, Clienn-Jung
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Abstract :
In this paper, a 32-bit tree-structured carry lookahead adder (CLA) is proposed by using the modified all-N-transistor (ANT) design. The 32-bit CLA not only possesses few transistor count, but also occupies small area size. Moreover, the post-layout simulation results given by TimeMill show that the clock used in this 32-bit CLA can run up to 1.25 GHz. The proposed architecture is also easily expanded for long data additions
Keywords :
adders; carry logic; circuit simulation; logic simulation; 1.25 GHz; 32 bit; TimeMill; area size; long data additions; modified all-N-transistor design; post-layout simulation results; tree-structured carry lookahead adder; CMOS logic circuits; CMOS process; CMOS technology; Clocks; Computer science; Councils; Feedback; Logic design; Robustness; Signal generators;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922174
