Title :
A low power sinusoidal clock
Author :
Voss, Burkart ; Glesner, Manfred
Author_Institution :
Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
Abstract :
This paper describes a low power clock distribution that utilizes sinusoidal clock waveforms and proposes registers that are able to cope with the overlapping clock edges. We can report power savings of 30% to 70% compared with conventional clocking schemes while maintaining traditional static CMOS design styles and logic levels
Keywords :
CMOS digital integrated circuits; clocks; low-power electronics; logic levels; low power clock distribution; overlapping clock edges; power savings; sinusoidal clock; static CMOS design styles; CMOS logic circuits; Capacitance; Clocks; Frequency; Inductors; Microelectronics; Power supplies; RLC circuits; SPICE; Voltage;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922182
