A CMOS differential logic for low-power and high-speed applications

Author

Moisiadis, Yiannis ; Bouras, Ilias ; Arapoyanni, Angela

Author_Institution

Dept. of Inf., Athens Univ., Greece

Volume

4

fYear

2001

fDate

6-9 May 2001

Firstpage

140

Abstract

A new logic family called charge-sharing at precharge differential logic (CSPDL) is proposed. CSPDL utilises a charge-sharing scheme during the precharge phase. In order to equally charge the internal nodes to a voltage value lower than V_DD. In this way by recycling the stored charge, the power dissipation during the precharge phase is significantly reduced. Compared to other differential logic families adopting a recycling scheme, CSPDL requires no extra biasing voltages or complicated signaling schemes. Simulations demonstrate a power reduction of 30% and a delay improvement of 57% over the conventional dynamic DCVS logic

Keywords

CMOS logic circuits; delays; high-speed integrated circuits; low-power electronics; CMOS differential logic; CSPDL; charge-sharing at precharge differential logic; delay improvement; high-speed applications; internal nodes; low-power applications; power dissipation; CMOS logic circuits; Clocks; Delay; Logic circuits; Logic design; MOS devices; Power dissipation; Recycling; Switches; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922190

Filename

922190