A low-power 3-phase half rail pass-gate differential logic

The new three-phase half-rail pass-gate differential logic (HRPGDL) employs the charge recycling approach for low power, while eliminating the pre-evaluation problem using three-phase clocks and reduces transistor number due to pass-gate logic. The waveforms of several cascaded 2-input NAND gates indicate the possibility of over 1 GHz operation at supply voltage of 3V using standard CMOS 0.35 μm technology. The improvement over other dynamic logic in terms of delay and power-delay product for 3-input NAND gates is also demonstrated