Title :
CRRDL: a novel charge recovery-recycling differential logic
Author_Institution :
Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon
Abstract :
This paper describes a dynamic CMOS charge recovery and recycling differential logic (CRRDL), which combines adiabatic switching and charge recycling techniques with conventional differential logic circuits for the design of power-efficient computation. In CRRDL, charges at the high capacitance output nodes are first recovered from a pulsed power clock supply and then recycled for evaluation. Simulation results show that CRRDL demonstrates a better power-delay product than other differential logic circuits
Keywords :
CMOS logic circuits; VLSI; capacitance; delays; integrated circuit design; low-power electronics; CRRDL; adiabatic switching; charge recovery-recycling differential logic; charge recycling techniques; dynamic CMOS; high capacitance output nodes; power-delay product; power-efficient computation; pulsed power clock supply; CMOS logic circuits; Capacitance; Circuit simulation; Clocks; Computational modeling; Logic circuits; Logic design; Pulsed power supplies; Recycling; Switching circuits;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922194
