CRRDL: a novel charge recovery-recycling differential logic

This paper describes a dynamic CMOS charge recovery and recycling differential logic (CRRDL), which combines adiabatic switching and charge recycling techniques with conventional differential logic circuits for the design of power-efficient computation. In CRRDL, charges at the high capacitance output nodes are first recovered from a pulsed power clock supply and then recycled for evaluation. Simulation results show that CRRDL demonstrates a better power-delay product than other differential logic circuits