DocumentCode
1745224
Title
A regular parallel multiplier which utilizes multiple carry-propagate adders
Author
Eriksson, Heizrik ; Larsson-Edefors, Per ; Marnane, W.P.
Author_Institution
Dept. of Phys., Linkoping Univ., Sweden
Volume
4
fYear
2001
fDate
6-9 May 2001
Firstpage
166
Abstract
A new regular partial-product reduction tree for parallel multipliers is presented in this paper. The reduction tree has a simple and efficient interconnect configuration and a minimal hardware usage. The reduction tree has a gate structure, which allows for extensive use of carry-propagation adders. Since carry-propagation adders can be very efficiently implemented, significant delay reduction is expected for large multipliers
Keywords
adders; multiplying circuits; trees (mathematics); carry-propagate adder; gate structure; hardware usage; interconnect configuration; parallel multiplier; regular partial-product reduction tree; time delay; Adders; Compressors; Delay; Educational institutions; Fabrication; Hardware; Integrated circuit interconnections; Organizing; Physics; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location
Sydney, NSW
Print_ISBN
0-7803-6685-9
Type
conf
DOI
10.1109/ISCAS.2001.922198
Filename
922198
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