Title :
Strategies for on-chip sub-nanosecond signal capture and timing measurements
Author :
Abaskharoun, Naznzy ; Hafed, Mohamed ; Roberts, Gordon W.
Author_Institution :
Microelectron. & Comput. Syst. Lab., McGill Univ., Montreal, Que., Canada
Abstract :
Two strategies for on-chip signal capture and characterization are described. The first is an extension of an integrated mixed-signal test core that has the ability to provide time and frequency domain measurements. This extension consists of a Delay Locked Loop (DLL) based timing module that through an undersampling algorithm provides high effective sampling rates for arbitrary, high bandwidth, periodic signals. The second is a time to digital converter (TDC) based on a Vernier Delay Line (VDL). This circuit can sample digital signals at very fine time intervals, and produce an on-chip jitter cumulative distribution function (CDF) from which a jitter histogram may be extracted. Both techniques were successfully demonstrated using a prototype IC in a 0.35 μm CMOS process
Keywords :
CMOS integrated circuits; analogue-digital conversion; delay lines; delay lock loops; integrated circuit testing; mixed analogue-digital integrated circuits; signal sampling; timing circuits; timing jitter; 0.35 micron; CMOS IC; Vernier delay line; cumulative distribution function; delay locked loop; histogram; integrated mixed-signal test; jitter measurement; on-chip signal capture; periodic signal sampling; sub-nanosecond resolution; time-to-digital converter; timing module; undersampling algorithm; Bandwidth; Delay effects; Frequency domain analysis; Frequency measurement; Integrated circuit measurements; Jitter; Sampling methods; Testing; Time measurement; Timing;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922200
