Strategies for on-chip sub-nanosecond signal capture and timing measurements

Two strategies for on-chip signal capture and characterization are described. The first is an extension of an integrated mixed-signal test core that has the ability to provide time and frequency domain measurements. This extension consists of a Delay Locked Loop (DLL) based timing module that through an undersampling algorithm provides high effective sampling rates for arbitrary, high bandwidth, periodic signals. The second is a time to digital converter (TDC) based on a Vernier Delay Line (VDL). This circuit can sample digital signals at very fine time intervals, and produce an on-chip jitter cumulative distribution function (CDF) from which a jitter histogram may be extracted. Both techniques were successfully demonstrated using a prototype IC in a 0.35 μm CMOS process