Title :
Modified SRCMOS cell for high-throughput wave-pipelined arithmetic units
Author :
Säntti, Tero ; Isoaho, Jouini
Author_Institution :
Lab. of Electron. & Inf. Technol., Turku Univ., Finland
Abstract :
In this paper a modified basic cell for wave-pipelines is proposed. The cell is self resetting and has complementary outputs. Simulations of the cell demonstrate that delay variations for all input combinations are small, and the cell´s sensitivity to pulse length variation is reduced. 8×8 and 16×16-bit multipliers are designed using 0.35 μm 2.5 V CMOS technology. The proposed units display a cycle time of 620 ps, corresponding to maximum operation frequency of 1.6 GHz
Keywords :
CMOS logic circuits; multiplying circuits; pipeline arithmetic; 0.35 micron; 1.6 GHz; 16 bit; 2.5 V; 620 ps; 8 bit; SRCMOS cell; cycle time; multiplier; self-resetting CMOS technology; throughput; wave-pipelined arithmetic unit; Arithmetic; CMOS technology; Clocks; Delay; Frequency; Information technology; Laboratories; Modems; Pipelines; Signal processing;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922205
