Title :
An embedded low power FIR filter
Author :
Xu, Gang ; Yuan, Jiren
Author_Institution :
Competence Centre for Circuit Design, Lund Univ., Sweden
Abstract :
A new sampler with embedded FIR filter was designed with the charge sampling technique. The filter functions by summing the weighted current on a passive capacitor and the weighting factors are decided by the FIR coefficients. The performance of the filter can well compete with conventional analog filter but with smaller area and less power consumption. A testing chip was designed with 2 V supply, 7 mW power consumption and 0.4 mm2 area in 0.35 μm CMOS technology
Keywords :
CMOS integrated circuits; FIR filters; analogue-digital conversion; embedded systems; low-power electronics; 0.35 micron; 2 V; 7 mW; CMOS technology; charge sampling circuit; embedded low-power FIR filter; passive capacitor; weighting factor; Capacitors; Circuit synthesis; Clocks; Energy consumption; Finite impulse response filter; Frequency; Image sampling; Passive filters; Sampling methods; Voltage;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922214
