A multi-gigabit CMOS data recovery circuit using an analog parallel sampling technique

A CMOS clock and data recovery circuit for multi-gigabit data rates is described. It uses a multiphase PLL and parallel sampling techniques to reduce the speed requirements on the circuits. A parallel phase detection technique that results in linear loop control and improves loop stability is introduced. We present a new charge-pump circuit that encodes phase error into current amplitude, eliminating the problem of creating precise timing pulses to control switches. The proposed circuit was designed using TSMC 0.35 μm process parameters and verified by simulations under the presence of channel distortion and switching noise. Simulation results show that the circuit is capable of recovering clock and data at a speed of 2 Gbps