A CMOS clock and data recovery with two-XOR phase-frequency detector circuit

Author

Kang, Jin-Ku ; Dong-Hee Kim

Author_Institution

Dept. of Electr. & Comput. Eng., Inha Univ., Inchon, South Korea

Volume

4

fYear

2001

fDate

6-9 May 2001

Firstpage

266

Abstract

This paper describes a 1.0 Gbps Clock and Data Recovery circuit with a simple PFD structure. The proposed circuit is based on a single loop controlled by a Phase Frequency Detector (PFD) which has two-XOR gates. The VCO composed of four differential buffer stages generates eight differential clocks each spaced by 45°. The PFD generates the VCO control signal by comparing two different phase clocks and input data. The circuit operates on 800 Mbps to 1.2 Gbps data rate under 2.5 V supply using 0.25 μm-CMOS HSPICE simulation. The circuit is under fabrication. The measured results are presented

Keywords

CMOS digital integrated circuits; SPICE; buffer circuits; circuit simulation; phase detectors; synchronisation; 0.25 micron; 1.0 Gbit/s; 2.5 V; 800 Mbit/s to 1.2 Gbit/s; CMOS clock and data recovery; HSPICE simulation; PFD structure; data rate; differential buffer stages; differential clocks; phase clocks; two-XOR phase-frequency detector circuit; Charge pumps; Circuits; Clocks; Delay; Filters; Logic gates; Phase detection; Phase frequency detector; Signal generators; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922223

Filename

922223