VLSI considerations in the design of k-ary n-cube interconnection networks

In this paper, we introduce a new VLSI complexity measure for the k-ary n-cube direct interconnection networks. The new measure, called the peak wire density, P, takes into account the contribution of all network dimensions in the channel width. We develop analytical models for the base network latency under the proposed measure assuming both the wormhole and the store-and-forward switching mechanisms. Our experimental results show that under the peak wire density, low dimension networks achieve the least latency. We also consider the network area and show that using the newly introduced measure, moderate dimension networks (n=3 or 4) achieve the least latency. Moreover, we compare networks based on the more traditional AT² performance measure and assuming the introduced peak wire density measure. Our results show that moderate dimension networks achieve the least AT² values