Title :
Customizable DSP architecture for ASIP core design
Author :
Bajot, Yann ; Mehrez, Habib
Author_Institution :
Lab. LIP6/ASIM, Paris VI Univ., France
Abstract :
We present in this paper a configurable DSP architecture and its associated software framework intended to be used in ASIP core design. This architecture aims to speed up the execution of a well-defined target application and minimize the hardware cost. It is based on a configurable and modular model that makes the most of intrinsic ILP of the application by the use of specialized functional units and VLIW instructions. Implementation results of a complex application, the GSM EFR encoder algorithm, shows the efficiency of the customized architecture
Keywords :
digital signal processing chips; parallel architectures; reconfigurable architectures; speech coding; ASIP core design; DSP; GSM EFR encoder algorithm; ILP; VLIW instruction; configurable modular model; customized architecture; software framework; Application software; Application specific processors; Arithmetic; Computer architecture; Concurrent computing; Costs; Digital signal processing; GSM; Hardware; VLIW;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922232
