A VLSI architecture of a piecewise RBF decision feedback channel equalizer

This paper proposes a VLSI architecture for a decision feedback channel equalizer based on the Radial Basis Functions (RBF-DFE). The performance of this method approximates that of the optimal equalizer based on the maximum likelihood estimation (MLSE). The regularity of the operation structure makes possible a parallel implementation. The Gaussian characteristic of the RBF-DFE is approximated by a piecewise linear-function (PL-RBF-DFE) to propose a digital architecture. The PL-RBF-DFE equalizer was simulated and synthesized in CMOS 0.5 μm technology. A throughput of 20 Mbits/s, over a surface occupied by 16,200 transistors (without memory area), was achieved for a parallel architecture. The proposed architectures are applicable in adaptive and blind channel equalization