Design and implementation of channel equalizers for block transmission systems

We investigate the channel equalization schemes for block transmission systems applied in mobile radio communication. The channel equalization process is first formulated based on Cholesky decomposition. Various equalizer architectures subject to different optimization criteria are next derived. Simulation results indicate the superiority of MMSE block DFE structure over others. For its hardware design, we adopt Schur algorithm and develop an efficient Toeplitz solver to perform the Cholesky decomposition. Combined with the matched filtering and the DFE architectures, the derived channel equalizer features a highly parallel, hardware efficient and scalable design. The design is verified by a Xilinx Virtex FPGA and can achieve a processing rate up to 3M symbols per second