Design and implementation of channel equalizers for block transmission systems

Author

Hwang, Yin-Tsung ; Han, Jih-Cheng ; Liu, Jing-Yi

Author_Institution

Dept. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Yulin, Taiwan

Volume

4

fYear

2001

fDate

6-9 May 2001

Firstpage

354

Abstract

We investigate the channel equalization schemes for block transmission systems applied in mobile radio communication. The channel equalization process is first formulated based on Cholesky decomposition. Various equalizer architectures subject to different optimization criteria are next derived. Simulation results indicate the superiority of MMSE block DFE structure over others. For its hardware design, we adopt Schur algorithm and develop an efficient Toeplitz solver to perform the Cholesky decomposition. Combined with the matched filtering and the DFE architectures, the derived channel equalizer features a highly parallel, hardware efficient and scalable design. The design is verified by a Xilinx Virtex FPGA and can achieve a processing rate up to 3M symbols per second

Keywords

Toeplitz matrices; decision feedback equalisers; field programmable gate arrays; least mean squares methods; matched filters; matrix decomposition; mobile radio; Cholesky decomposition; MMSE DFE architecture; Schur algorithm; Toeplitz solver; Xilinx Virtex FPGA; block transmission system; channel equalizer; hardware design; matched filtering; mobile radio communication; optimization; Algorithm design and analysis; Blind equalizers; Channel estimation; Decision feedback equalizers; Hardware; Land mobile radio; Matched filters; Maximum likelihood detection; Maximum likelihood estimation; Performance evaluation;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922246

Filename

922246