Title :
Low-voltage swing clock distribution schemes
Author :
Zhu, Q.K. ; Zhang, M.
Author_Institution :
Intel Corp., Castro Valley, CA, USA
Abstract :
This paper proposes two schemes for the low-voltage swing clocks in global and local clock distributions. These schemes provide about 50% total clocking power reduction or about 25%, full-chip power reduction in a microprocessor case. The circuit structures and operation principles for low-and-high swing voltage conversions are presented. It also includes a latch with four clock lines in half-Vdd swings. A USA patent has been granted for the proposed schemes
Keywords :
clocks; integrated circuit design; low-power electronics; microprocessor chips; full-chip power reduction; global clock distributions; half-Vdd swings; local clock distributions; low-voltage swing clocks; microprocessor; total clocking power reduction; Capacitors; Clocks; Driver circuits; Energy consumption; Frequency; Latches; Phase locked loops; Power distribution; Very large scale integration; Voltage;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922262
