A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty

The design of clock distribution networks in synchronous systems presents enormous challenges. Control of the clock signal delay in the presence of various noise sources, process parameter variations, and environmental effects represents one of the fundamental problems in the design of high speed synchronous circuits. An algorithm that improves the tolerance of a clock distribution network to process and environmental variations is presented in this paper. The algorithm generates a clock tree topology that minimizes the uncertainty of the clock signal delay in the most critical data paths. Details of the algorithm and preliminary results on benchmark circuits are presented