Title :
Minimizing process-induced skew using delay tuning
Author :
Nekili, M. ; Savaria, Y. ; Bois, G.
Author_Institution :
Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
Abstract :
Tolerance to process-induced skew remains one of the major concerns in large-area and high-speed clock distribution networks. Indeed, despite the availability of some efficient exact-zero skew algorithms that can be applied during circuit design, the skew remains an important performance limiting factor after chip manufacturing. This paper presents techniques to minimize this kind of skew using delay tuning in buffered clock trees
Keywords :
circuit tuning; clocks; delays; high-speed integrated circuits; integrated circuit design; buffered clock trees; chip manufacturing; circuit design; delay tuning; high-speed clock distribution networks; large-area clock distribution networks; performance limiting factor; process-induced skew; Availability; Calibration; Capacitors; Circuit synthesis; Clocks; Delay; Integrated circuit interconnections; Laser tuning; Manufacturing; Testing;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922264
