Title :
Non-linearity reduction technique for delay-locked delay-lines
Author :
Fanucci, L. ; Roncella, R. ; Saletti, R.
Author_Institution :
Dipartimento di Ingegneria dell´´Inf: Elettronica, Inf., Telecommun., Nat. Res. Council, Pisa, Italy
Abstract :
A reduction of the nonlinearity of a CMOS all-digital shunt-capacitor delay-locked delay-line (DLL) is achieved by performing a statistical test on the line and correcting the individual cell delay mismatch according to the test results. A fully digital cell controller efficiently realizing the technique is described. Simulation results show the feasibility of the technique and the significant reduction of the nonlinearity obtained with only four additional shunt capacitor couples per cell
Keywords :
CMOS digital integrated circuits; cellular arrays; delay lines; delay lock loops; integrated circuit testing; CMOS all-digital shunt-capacitor DLL; cell delay mismatch; delay-locked delay-lines; nonlinearity reduction technique; shunt capacitor couples; statistical test; CMOS technology; Capacitors; Circuit simulation; Clocks; Councils; Delay lines; Linearity; Particle measurements; Telecommunications; Time measurement;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922265
