Enhanced low power motion estimation VLSI architectures for video compression

Author

Elgamel, Mohamed A. ; Shams, Ahmed M. ; Xueling, Xi ; Bayoumi, Magdy A.

Author_Institution

Center for Adv. Comput. Studies, Louisiana Univ., Lafayette, LA, USA

Volume

4

fYear

2001

fDate

6-9 May 2001

Firstpage

474

Abstract

Power consumption is very critical for portable video applications. During compression, the largest portion of power is consumed in the Motion Estimation part, which requires a huge amount of computation. This paper presents an architectural enhancement to reduce the power consumption during full-search block-matching (FSBM) motion estimation without sacrificing throughput or optimality. The proposed approach achieves these power savings by disabling portions of the architecture that perform unnecessary computations. A comparison between our enhancement and others is presented based on simulation and analytical analysis. Different benchmarks are used to test and compare the discussed architectures. Analytical and simulation results show the effectiveness of the enhancements

Keywords

VLSI; data compression; low-power electronics; motion estimation; systolic arrays; video coding; full-search block-matching algorithm; low-power VLSI architecture; motion estimation; portable video; power consumption; systolic array; video compression; Analytical models; Computational modeling; Computer architecture; Energy consumption; Motion estimation; Throughput; Transform coding; Very large scale integration; Video coding; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922277

Filename

922277