Fast system-level exploration of memory architectures driven by energy-delay metrics

This paper proposes a system-level methodology for the fast exploration of memory architectures from an energy-delay perspective. The aim is to find a near-optimal configuration of the cache architecture without performing the exhaustive analysis of the parameter space (mainly cache size, block size and associativity). The paper proposes an heuristic method to reduce the time spent to simulate different system configurations, during the execution of different applications. The method is based on the sensitivity analysis of the system behavior with respect to the variation of the relevant system-level parameters. The analysis exploits dynamic profiling of memory references on system-level buses. The traces are applied to a parametric model of the system, including system-level buses and multi-level memory hierarchy models. The benefits of the proposed methodology have been demonstrated through the design of a real-world example: a MicroSPARC2-based system running the Mediabench suite. Experimental results have shown that the design exploration phase can achieve a speedup of 585% while identifying the optimal or near-optimal system-level configuration with an average error of 5.11% at most