A low power charge-recycling ROM architecture

Author

Yang, Byung-Do ; Kim, Lee-Sip

Author_Institution

Dept. of EECS, Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea

Volume

4

fYear

2001

fDate

6-9 May 2001

Firstpage

510

Abstract

A new low power charge recycling ROM (CR-ROM) architecture is proposed. The CR-ROM uses charge-recycling method in bit lines of ROM to save the power consumption. About 90% of the total power used in the ROM is consumed in bit lines. With the proposed method, power consumption in ROM bit lines can be reduced asymptotically to zero if the number of bit lines is infinite and the sense amplifiers detect infinitely small voltage difference. However, the real sense amplifiers cannot sense very small voltage difference. Therefore, reduction of power consumption is limited. The simulation results show that the CR-ROM only consumes 13%~78% of the conventional low power contact programming mask ROM

Keywords

low-power electronics; memory architecture; read-only storage; bit line; low-power charge-recycling ROM architecture; power consumption; sense amplifier; Capacitance; Clocks; Computational modeling; Energy consumption; Personal digital assistants; Power amplifiers; Read only memory; Recycling; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922286

Filename

922286