Title :
A low complexity FEC design for DAB
Author :
Kim, Ju Byoung ; Lim, Young Jin ; Lee, Moon Ho
Author_Institution :
Inst. of Inf. & Commun., Chonbuk Nat. Univ., Chonju, South Korea
Abstract :
In this paper, because of FEC block hardware size in DAB system, is considered to have the benefit of efficient usage. A Proposed architecture has only 8 GF-multipliers and 4 GF-adders in RS coder, 2 RAM(128) and 4 RAM(256) in convolutional interleaver. We have designed FEC block for DAB system and have implemented on Altera-FPGA chip(FLEX 10K) successfully.
Keywords :
Reed-Solomon codes; audio coding; communication complexity; convolutional codes; digital audio broadcasting; field programmable gate arrays; forward error correction; interleaved codes; Altera-FPGA chip; FLEX10K; GF-adder; GF-multiplier; RAM; Reed-Solomon coder; convolutional interleaver; digital audio broadcasting; forward error correction; hardware architecture; low-complexity FEC block design; Convolutional codes; Decoding; Digital video broadcasting; Error correction; Forward error correction; Polynomials; Telecommunication standards;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW, Australia
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922289
